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| TEA6422 BUS-CONTROLLED AUDIO MATRIX s s s s s s s s s 6 Stereo Inputs 3 Stereo Ouputs Gain Control 0 dB/Mute for each Output Cascadable (2 different addresses) Serial Bus Controlled Very Low Noise Very Low Distorsion Fully ESD Protected Wide Audio Dynamic Range ( 3 VRMS) SHRINK DIP24 (Shrink Plastic Package) ORDER CODE: TEA6422 DESCRIPTION The TEA6422 switches 6 stereo audio inputs on 3 stereo outputs. All the switching possibilities are changed through the I2C BUS. SO28 (Plastic Monopackage) ORDER CODE: TEA6422D Figure 1. PIN CONNECTIONS SO28 SDIP24 GND GND CAPACITANCE VS L1 L2 L3 L4 L5 L6 LOUT1 ROUT1 LOUT2 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SDA SCL ADDR R1 R2 R3 NC NC R4 R5 R6 ROUT3 LOUT3 ROUT2 24 23 22 21 20 19 18 17 16 15 14 13 SDA SCL ADDR R1 R2 R3 R4 R5 R6 ROUT3 LOUT3 ROUT2 CAPACITANCE VS L1 L2 L3 NC NC L4 L5 L6 LOUT1 ROUT1 LOUT2 September 2003 1/10 1 TEA6422 BLOCK DIAGRAM RIGHT INPUTS GAIN = 0 dB RIGHT OUTPUTS VS C GND SUPPLY BUS DECODER SDA SCL ADDR LEFT OUTPUTS GAIN = 0 dB LEFT INPUTS ABSOLUTE MAXIMUM RATINGS Symbol VCC Toper Tstg Parameter Supply Voltage Operating Temperature Storage Temperature Value 12 0, + 70 - 20, + 150 Unit V oC oC THERMAL DATA Symbol Rth(j-a) Parameter Junction - ambient Thermal Resistance SDIP24 SO28 Value 75 75 Unit C/W oC/W o 2/10 1 TEA6422 ELECTRICAL CHARACTERISTICS TA = 25 oC, VS = 9 V, RL = 10 k, RG = 600 , f = 1 kHz (unless otherwise specified) Symbol SUPPLY VS IS SVR MATRIX VIN RI CS VOUT ROUT eNI S/N G d VCL RL Input DC Level Input Resistance Channel Separation VIN = 2VRMS, f = 1kHz 30 80 VCC/2 50 90 100 V k dB Supply Voltage Supply Current Ripple Rejection VIN = 500mVRMS, f = 1kHz 70 8 10 3 80 11 8 V mA dB Parameter Test Conditions Min. Typ. Max. Unit OUTPUT BUFFER Output DC Level Output Resistance Input Noise Signal to Noise Ratio Gain Distortion Clipping Level Output Load Resistance VIN = VOUT = 1VRMS d = 0.3 %, VS = 10 V 2.8 2 BW = 20 - 20kHz, flat VIN = VOUT = 1VRMS -1 VCC/2 50 3 110 0 0.01 3 +1 0.05 100 V V dB dB % VRMS k 3/10 1 TEA6422 I2C BUS CHARACTERISTICS Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low-to High Transition - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400 V V A pF ns ns V ns pF s s ns ns s s s s Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 100 1000 300 10 V V A kHz ns ns pF Parameter Test Conditions Min. Max. Unit VI = 0 to VCC 1.5V to 3V 3V to 1.5V VI = 0 to VCC 1.5V to 3V 3V to 1.5V IOL = 3mA 3V to 1.5V 4.7 4.0 250 0 4.0 4.7 4.0 4.7 340 Figure 2. IC Bus Timing SDA t BUF t LOW tf SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT SDA t SU,STA t SU,STO (start, stop) 4/10 1 TEA6422 POWER ON RESET After power-on reset all outputs are in mute mode Symbol Reset End of Reset Parameter Start of Reset Conditions Incr. VCC Decr. VCC Incr. VCC Min. Typ. Max. 2.5 4.2 Unit V V V 4.5 SOFTWARE SPECIFICATION 1. Chip address Address 1001 1000 1001 1010 HEX 98 9A ADDR 0 1 2. Data bytes Output select 0 0 1 0 1 0 Output 1 Output 2 Output 3 X X X I2 I1 I0 Input select 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Mute X Q1 Q0 X X X = don't care - MSB is transmitted first Example : 010XX100 connects output 3 with input 5. 5/10 1 TEA6422 Figure 3. Distorsion Level versus Input Voltage dis (%) 0.1 0.08 0.06 0.04 0.02 0 2.4 2.5 2.6 2.7 2.8 2.9 3.0 VIN (V RMS ) V S = 10 V f = 1 kHz T amb = 25 C Figure 5. Clipping Level versus Supply Voltage 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 7.5 8 8.5 9 9.5 10 VS (V) 10.5 11 Vclipp ( VRMS ) dis = 0.3% f = 1 kHz Tamb = 25 C Figure 4. Supply Voltage Rejection versus Frequency ( VIN = 500 mVRMS) SVR (dB) 98 95 92 89 86 V S = 10 V 83 80 77 74 0.05 0.5 freq (kHz) 5 20 6/10 1 TEA6422 PIN CONFIGURATIONS (SDIP24 Package) Figure 6. Audio IN VC C Figure 8. Audio OUT VCC Pins 4-5-6-7-8-9 16-17-18-19-20- 21 L (R) x in x = 1, 2, 3, 4, 5, 6 50k Pins 10- 11-12 13-14-15 V C C /2 Matrix Point L (R) x out x = 1, 2, 3 Figure 7. ADDR Figure 9. Bus Inputs (SDA, SCL) VCC VCC 50k ESD PROT. 22 to CMOS Pins 23 - 24 VREF to CMOS X4 ACKN For SDA only Figure 10. TYPICAL APPLICATION (SDIP24 Package) 1 22 F +10V 3 100nF C1 C2 C3 Left Inputs C4 C5 C11 L R C H 2 Output L C12 C13 C14 22 2 24 23 SDA SCL Bus Inputs SW T 4 5 6 7 8 E A 6 4 2 2 21 20 19 18 17 16 15 14 13 C6 C7 C8 Right C9 C10 C18 C17 R C16 C15 L R C H 2 Output C H 3 Output Inputs 9 10 11 12 C H 1 Output 7/10 TEA6422 PACKAGE MECHANICAL DATA 24 PINS - PLASTIC SHRINK Figure 11. 24-Pin Shrink Plastic Dual In Line Package E E1 Dim. A mm Min 0.51 3.05 0.36 0.76 0.23 Typ Max 5.08 0.020 Min inches Typ Max 0.20 A1 A2 A A1 A2 B e1 e2 3.30 4.57 0.120 0.130 0.180 0.46 0.56 0.014 0.018 0.022 2 1 0 0.009 0.009 0.015 0 8 0 0.30 0.070 0.30 10.92 1.52 Number of Pins 24 0.430 0.060 0.340 Stand-off B B1 e L B1 C D 1.02 1.14 0.030 0.040 0.045 0.25 0.38 c D E 22.61 22.86 23.11 0.890 0.90 0.910 7.62 6.10 1.778 7.62 8.64 6.40 6.86 0.240 0.252 0.270 E E1 e 24 13 F .015 0,38 Gage Plane e1 e2 e3 N 1 12 e3 SDIP24 e2 8/10 TEA6422 PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE Figure 12. 28-Pin Plastic Small Outline Package, 300-mil Width Dim. A A1 B C D E e H h K L G SO28 N mm Min 2.35 0.10 0.33 0.23 17.70 7.40 1.27 10.01 0.25 0.41 10.64 0.394 0.74 0.010 0 1.27 0.016 0.10 Typ Max Min 2.65 0.0926 0.30 0.0040 0.51 0.013 0.32 0.0091 18.10 0.6969 7.60 0.2914 inches Typ Max 0.1043 0.0118 0.020 0.0125 0.7125 0.2992 0.0500 0.419 0.029 8 0.050 0.004 28 Number of Pins 9/10 TEA6422 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 10/10 |
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